1. Field of the Invention
The present invention relates to a semiconductor device comprising an epitaxial layer. More particularly, the present invention relates to a multi-layered structure including an epitaxial layer, to a semiconductor device comprising the same, and to a method of fabricating the semiconductor device.
2. Description of the Related Art
Recently, the use tensile-strained silicon as a channel layer has been researched as a way to improve carrier mobility in a field effect transistor (hereinafter, referred to as a FET).
In general, the tensile-strained silicon channel layer is produced by forming an Si1-xGex virtual substrate on a silicon substrate, annealing the resultant structure to relax the structure, and forming a silicon channel layer on the relaxed Si1-xGex virtual substrate. As a result, the tensile-strained silicon channel layer can be obtained by using the tensile strain in silicon caused by a lattice mismatch between the relaxed Si1-xGex virtual substrate and the silicon channel layer.
In forming the Si1-xGex virtual substrate on the silicon substrate, dislocations thread within the Si1-xGex virtual substrate when the strain caused by the lattice mismatch with the silicon substrate is relaxed. The threads of the dislocations in the virtual substrate accumulate at the top portion of the virtual substrate, and propagate into the silicon channel, thereby causing carrier scattering to occur in the channel. Carrier scattering prevents the FET from providing high carrier mobility.
An attempt to reduce the dislocation defect density of the epitaxial layer is described in U.S. Pat. No. 5,659,187. The patent discloses that an epitaxial layer, used as a virtual substrate, and having a composition graded by 0.025 to 2% per 1,000 Å in its direction of thickness, has a reduced dislocation defect density.
Meanwhile, in order to form a tensile-strained silicon channel layer that provides sufficient carrier mobility at the top of an Si1-xGex virtual substrate, the value of X at the top surface of the Si1-xGex virtual substrate must be 0.2 or more. And preferably, the value of X at the bottom surface of the Si1-xGex virtual substrate contiguous to (i.e., interfacing with) the silicon substrate is 0.
Therefore, in a case in which an Si1-xGex layer is used as the virtual substrate, and the composition of the Si1-xGex was graded by 2% per 1,000 Å as described in the above-mentioned patent, the Si1-xGex virtual substrate would have to be at least 1 μm thick if the value of X were to be 0 at the bottom surface and 0.2 or more at the top surface. Such a thick epitaxial layer presents problems in implementing a subsequent photolithography process.
Another attempt to reduce the dislocation defect density, proposes a chemical mechanical polishing (CMP) process to eliminate the threads of the dislocations accumulating at the top portion of the epitaxial layer.
Nonetheless, despite the use of the above-described methods, the dislocation defect density of an Si1-xGex virtual substrate remains high—on the order of 106/cm2.